In the fabrication of integrated circuits and other electronic devices, multiple layers of conducting, semiconducting, and dielectric materials are deposited onto or removed from a substrate surface. As layers of materials are sequentially deposited onto and removed from the substrate, the uppermost surface of the substrate may become non-planar and require planarization. Planarizing a surface, or “polishing” a surface, is a process where material is removed from the surface of the substrate to form a generally even, planar surface. Planarization is useful in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials. Planarization also is useful in forming features on a substrate by removing excess deposited material used to fill the features and to provide an even surface for subsequent levels of metallization and processing.
Compositions and methods for planarizing or polishing the surface of a substrate are well known in the art. Chemical-mechanical planarization, or chemical-mechanical polishing (CMP), is a common technique used to planarize substrates. CMP utilizes a chemical composition, known as a CMP composition or more simply as a polishing composition (also referred to as a polishing slurry), for selective removal of material from the substrate. Polishing compositions typically are applied to a substrate by contacting the surface of the substrate with a polishing pad (e.g., polishing cloth or polishing disk) saturated with the polishing composition. The polishing of the substrate typically is further aided by the chemical activity of the polishing composition and/or the mechanical activity of an abrasive suspended in the polishing composition or incorporated into the polishing pad (e.g., fixed abrasive polishing pad).
As the size of integrated circuits is reduced and the number of integrated circuits on a chip increases, the components that make up the circuits must be positioned closer together in order to comply with the limited space available on a typical chip. Effective isolation between circuits is important for ensuring optimum semiconductor performance. To that end, shallow trenches are etched into the semiconductor substrate and filled with insulating material to isolate active regions of the integrated circuit. More specifically, shallow trench isolation (STI) is a process in which a silicon nitride layer is formed on a silicon substrate, shallow trenches are formed via etching or photolithography, and a dielectric layer is deposited to fill the trenches. Due to variation in the depth of trenches formed in this manner, it is typically necessary to deposit an excess of dielectric material on top of the substrate to ensure complete filling of all trenches. The dielectric material (e.g., a silicon oxide) conforms to the underlying topography of the substrate.
Thus, after the dielectric material has been placed, the surface of the deposited dielectric material is characterized by an uneven combination of raised areas of the dielectric material separated by trenches in the dielectric material, the raised areas and trenches of the dielectric material aligning with corresponding raised areas and trenches of the underlying surface. The region of the substrate surface that includes the raised dielectric material and trenches is referred to as a pattern field of the substrate, e.g., as “pattern material,” “pattern oxide,” or “pattern dielectric.” The pattern field is characterized by a “step height,” which is the difference in height of the raised areas of the dielectric material relative to the trench height.
The excess dielectric material is typically removed by a CMP process, which additionally provides a planar surface for further processing. During removal of the raised area material, an amount of material from the trenches also will be removed. This removal of material from the trenches is referred to as “trench erosion” or “trench loss.” Trench loss is the amount (thickness, e.g., in Angstroms (Å)) of material removed from trenches in achieving planarization of pattern dielectric material by eliminating an initial step height. Trench loss is calculated as the initial trench thickness minus a final trench thickness. Desirably, the rate of removal of material from trenches is well below the rate of removal from raised areas. Thus, as material of the raised areas is removed (at a faster rate compared to material being removed from the trenches) the pattern dielectric becomes a highly planarized surface that may be referred to as a “blanket” region of the processed substrate surface, e.g., “blanket dielectric” or “blanket oxide.”
A polishing composition can be characterized according to its polishing rate (i.e., removal rate) and its planarization efficiency. The polishing rate refers to the rate of removal of a material from the surface of the substrate and is usually expressed in terms of units of length (thickness, e.g., in Angstroms (Å)) per unit of time (e.g., per minute). Different removal rates relating to different regions of a substrate, or to different stages of a polishing step, can be important in assessing process performance. A “pattern removal rate” is the rate of removal of dielectric material from raised areas of pattern dielectric layer at a stage of a process during which a substrate exhibits a substantial step height. “Blanket removal rate” refers to a rate of removal of dielectric material from planarized (i.e., “blanket”) areas of a pattern dielectric layer at an end of a polishing step, when step height has been significantly (e.g., essentially entirely) reduced. Planarization efficiency relates to step height reduction versus amount of material removed from the substrate (i.e., step height reduction divided by trench loss). Specifically, a polishing surface, e.g., a polishing pad, first contacts the “high points” of the surface and must remove material in order to form a planar surface. A process that results in achieving a planar surface with less removal of material is considered to be more efficient than a process requiring removal of more material to achieve planarity.
Often the rate of removal of the silicon oxide pattern material can be rate-limiting for the dielectric polishing step in STI processes, and therefore high removal rates of the silicon oxide pattern are desired to increase device throughput. However, if the blanket removal rate is too rapid, overpolishing of oxide in exposed trenches results in trench erosion and increased device defectivity. Overpolishing and associated trench loss can be avoided if the blanket removal rate is lowered.
It is desirable in certain polishing applications for a CMP composition to exhibit “self-stopping” behavior such that when a large percentage of the “high points” of the surface (i.e., raised areas) have been removed, the removal rate decreases. In self-stopping polishing applications, the removal rate is effectively high while a significant step height is present at the substrate surface and then the removal rate is lowered as the surface becomes effectively planar. In various dielectric polishing steps (e.g., of an STI process) the rate of removal of pattern dielectric material (e.g., dielectric layer) is typically a rate-limiting factor of the overall process. Therefore, high removal rates of pattern dielectric material are desired to increase throughput. Good efficiency in the form of relatively low trench loss is also desirable. Further, if the removal rate of dielectric remains high after achieving planarization, overpolishing occurs, resulting in added trench loss.
Advantages of self-stopping slurries result from the reduced blanket removal rate, which produces a wide endpoint window. For example, self-stopping behavior allows for polishing of substrates having reduced dielectric film thickness, allowing for a reduced amount of material to be deposited over a structured lower layer. Also, motor torque endpoint detection can be used for more effective monitoring of final topography. Substrates can be polished with lower trench loss by avoiding overpolishing or unnecessary removal of dielectric after planarization.
Self-stopping CMP compositions currently have been developed based on ceria/anionic polyelectrolyte systems. For example, U.S. Patent Application Publication 2008/0121839 discloses a polishing composition comprising inorganic abrasives, polyacrylic acid/maleic acid copolymer, and gemini surfactant. Korean Patent No. 10-1524624 discloses a polishing composition comprising ceria, a carboxylic acid, and mixed amine compounds (English-language abstract). International Patent Application Publication No. WO 2006/115393 discloses a polishing composition comprising ceria, a hydroxycarboxylic acid, and an amino alcohol. However, as the structure of semiconductor devices becomes more complicated and especially as NAND technology is moved from 2D to 3D, current self-stopping CMP compositions, due to the use of anionic polymer, are being challenged by the limited step height reduction rate brought about by electrostatic repulsion between the abrasive and the silicon oxide surface.
A need remains for compositions and methods for chemical-mechanical polishing of silicon oxide-containing substrates that will provide useful removal rates while also providing improved planarization efficiency. The invention provides such polishing compositions and methods. These and other advantages of the invention, as well as additional inventive features, will be apparent from the description of the invention provided herein.